Design of Novel Algorithm and Architecture for Feature Based Corner Detection for Image.

Abstract

A new algorithm has been developed for feature based corner detection for mosaicing images. Using this algorithm, a novel architecture suitable for FPGA/ASIC implementation has also been designed. The feature based corner detection technique proposed here is for extracting accurate corner positions than unstable corner points in existing algorithms. The design has been coded in Verilog conforming to RTL coding guidelines and fits in a single FPGA chip. The proposed design incorporates a high degree of pipelining and parallelism and hence offers high throughputs. The algorithm has also been coded in MATLAB in order to validate the hardware results. The Verilog design of the feature based corner detection architecture has been targeted on Xilinx Spartan6 xc6slx45-3fgg676 FPGA device. The design utilizes about 12,198 slices (58%) and the operating frequency is maximum of 292 MHz. The performance parameter PSNR has been computed for both the proposed and the existing methods for many number of mosaic images. The proposed method offers better reconstructed image quality and is 35 dB or more.