Design of Sliding Window Based Corner Detection Algorithm and Architecture for Image Mosaicing.

Abstract

new Sliding Window Based Corner Detection Algorithm has been developed for image mosaicing. Using this algorithm, a new architecture suitable for VLSI implementation has also been designed. The proposed design incorporates a high degree of pipelining and parallelism and hence offers high throughputs. The color image mosaicing is achieved by first convolving an original image using a 3x3 sliding window followed by smoothening the image using median filters. The design has been coded in Verilog as per RTL coding guidelines. The algorithm has also been coded in Matlab in order to validate the hardware results. The Verilog design of the proposed architecture for image mosaicing has been implemented on Xilinx Spartan 6 xc6slx45-3fgg676 FPGA device. The design utilizes about 144,858 gates and the operating frequency is about 100 MHz. The design is capable of processing high resolution color pictures of sizes of up to 1600×1200 pixels in real time.