Please use this identifier to cite or link to this item:
http://13.232.72.61:8080/jspui/handle/123456789/9677Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.date.accessioned | 2025-09-19T09:51:37Z | - |
| dc.date.available | 2025-09-19T09:51:37Z | - |
| dc.date.issued | 2025-07 | - |
| dc.identifier.uri | http://13.232.72.61:8080/jspui/handle/123456789/9677 | - |
| dc.language.iso | en | en_US |
| dc.publisher | VTU | en_US |
| dc.subject | Electronics and Communication | en_US |
| dc.subject | Question Papers | en_US |
| dc.subject | 3rd SEM | en_US |
| dc.title | Electronics and Communication Engineering June-July 2025 | en_US |
| dc.type | Other | en_US |
| Appears in Collections: | June-July 2025 | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Digital System Design-18EC34.pdf | 1.14 MB | Adobe PDF | View/Open | |
| Electronic Devices- 18EC33.pdf | 1.35 MB | Adobe PDF | View/Open | |
| Electronic Principles and Circuits- BEC303.pdf | 1.38 MB | Adobe PDF | View/Open | |
| Networks Analysis- BEC304.pdf | 2.1 MB | Adobe PDF | View/Open | |
| Power Electronics and Instrumentation- 18EC36.pdf | 1.05 MB | Adobe PDF | View/Open | |
| Basic signal Processing - 21EC33.pdf | 1.23 MB | Adobe PDF | View/Open | |
| Computer Organization and Architecture- BEC306C.pdf | 1.63 MB | Adobe PDF | View/Open | |
| Digital System Design using Verilog- BEC302.pdf | 1.91 MB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.