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http://13.232.72.61:8080/jspui/handle/123456789/989| Title: | Fault Tolerant Techniques for FPGAs: A Review |
| Authors: | Raghunath, B. H. Aravind, H. S. |
| Keywords: | Electronics Engineering Communication Look Up Table Application Specific Integrated Circuits |
| Issue Date: | Jul-2017 |
| Publisher: | Grenze Scientific Society |
| Citation: | Raghunath, B. H., & Aravind, H. S. (2017). Fault Tolerant Techniques for FPGAs: A Review. Kumar, M. et al.(Ed.), Int. Conf. on Signal, Image Processing Communication & Automation, ICSIPCA(pp. 415-418). Grenze Scientific Society: Bengaluru, India. |
| Abstract: | Field-Programmable Gate Arrays (FPGAs) have emerged as best option for d i g i t a l circuit implementation over the last few decades. FPGAs have the ability to reconfigure at runtime; therefore provide opportunities to overcome issues like reliability and availability which are the serious issues in safety critical applications. This review attempts to investigate some of popular methods in fault detection and also gives an overview of partial reconfiguration technique in FPGA based systems. |
| URI: | http://13.232.72.61:8080/jspui/handle/123456789/989 |
| ISBN: | 9781510856707 |
| Appears in Collections: | Conference Proceedings |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Fault Tolerant Techniques for FPGAs_ A Review.pdf | 208.2 kB | Adobe PDF | View/Open |
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