Please use this identifier to cite or link to this item:
http://13.232.72.61:8080/jspui/handle/123456789/989
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Raghunath, B. H. | - |
dc.contributor.author | Aravind, H. S. | - |
dc.date.accessioned | 2019-02-23T07:14:31Z | - |
dc.date.available | 2019-02-23T07:14:31Z | - |
dc.date.issued | 2017-07 | - |
dc.identifier.citation | Raghunath, B. H., & Aravind, H. S. (2017). Fault Tolerant Techniques for FPGAs: A Review. Kumar, M. et al.(Ed.), Int. Conf. on Signal, Image Processing Communication & Automation, ICSIPCA(pp. 415-418). Grenze Scientific Society: Bengaluru, India. | en_US |
dc.identifier.isbn | 9781510856707 | - |
dc.identifier.uri | http://13.232.72.61:8080/jspui/handle/123456789/989 | - |
dc.description.abstract | Field-Programmable Gate Arrays (FPGAs) have emerged as best option for d i g i t a l circuit implementation over the last few decades. FPGAs have the ability to reconfigure at runtime; therefore provide opportunities to overcome issues like reliability and availability which are the serious issues in safety critical applications. This review attempts to investigate some of popular methods in fault detection and also gives an overview of partial reconfiguration technique in FPGA based systems. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Grenze Scientific Society | en_US |
dc.subject | Electronics Engineering | en_US |
dc.subject | Communication | en_US |
dc.subject | Look Up Table | en_US |
dc.subject | Application Specific Integrated Circuits | en_US |
dc.title | Fault Tolerant Techniques for FPGAs: A Review | en_US |
dc.type | Other | en_US |
Appears in Collections: | Conference Proceedings |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Fault Tolerant Techniques for FPGAs_ A Review.pdf | 208.2 kB | Adobe PDF | View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.